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data sheet, rev. 3 may 2004 fw802b low-power phy ieee ? 1394 a-2000 two-cable transceiver/arbiter device ? distinguishing features compliant with ieee standard 1394 a-2000, ieee standard for a high performance serial bus amendment 1. low-power consumption during powerdown or microlow-power sleep mode. supports extended bias_handshake time for enhanced interoperability with camcorders. while unpowered and connected to the bus, the device will not drive tpbias on a connected port even if receiving incoming bias voltage on that port. does not require external filter capacitors for pll. does not require a separate 5 v supply for 5 v link controller interoperability. interoperable across 1394 ? cable with 1394 physi- cal layers (phy) using 5 v supplies. interoperable with 1394 link-layer controllers using 5 v supplies. 1394 a-2000 compliant common-mode noise filter on incoming tpbias. powerdown features to conserve energy in battery- powered applications include: ? device powerdown pin. ? link interface disable using lps. ? inactive ports power down. ? automatic microlow-power sleep mode during suspend. interface to link-layer co ntroller supports annex j electrical isolation as well as bus-keeper isolation. features provides two fully compliant cable ports at 100 mbits/s, 200 mbits/s, and 400 mbits/s. fully supports 1394 open hci requirements. supports arbitrated short bus reset to improve utilization of the bus. supports ack-accelerated arbitration and fly-by con- catenation. supports connection debounce. supports multispeed packet concatenation. supports phy pinging and remote phy access packets. fully supports suspend/resume. supports phy-link interface initialization and reset. supports 1394 a-2000 register set. supports lps/link-on as a part of phy-link inter- face. supports provisions of ieee 1394 -1995 standard for a high performance serial bus . fully interoperable with firewire ? implementation of ieee 1394 -1995. reports cable power fail interrupt when voltage at cps pin falls below 7.5 v. provides separate cable bias and driver termination voltage supply for each port. other features 64-pin tqfp package. (lead-free package also available. see ordering information on page 25.) single 3.3 v supply operation. data interface to link-layer controller provided through 2/4/8 parallel lines at 50 mbits/s. 25 mhz crystal oscillator and pll provide a 50 mhz link-layer controller clock as well as trans- mit/receive data at 100 mbits/s, 200 mbits/s, and 400 mbits/s. node power-class information signaling for system power management. multiple separate package signals provided for ana- log and digital supplies and grounds. description the agere systems inc. fw802b device provides the analog physical layer functions needed to imple- ment a two-port node in a cable-based ieee 1394 - 1995 and ieee 1394 a-2000 network. each cable port incorporates two differential line transceivers. the transceivers include circuitry to monitor the line conditions as needed for determin- ing connection status, for init ialization and arbitration, and for packet reception and transmission. the phy is designed to interface with a link-layer controller (llc).
2 2 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 table of contents contents page distinguishing features ....................................................................................................... ........................................1 features ...................................................................................................................... ................................................1 other features ................................................................................................................ ............................................1 description ................................................................................................................... ...............................................1 signal information ............................................................................................................ ...........................................6 application information ....................................................................................................... .......................................11 crystal selection considerations .............................................................................................. ................................12 load capacitance .............................................................................................................. ................................13 adjustment to crystal loading ................................................................................................. ..........................13 crystal/board layout .......................................................................................................... ................................13 1394 application support contact information ...................................................................................... ....................13 absolute maximum ratings ...................................................................................................... .................................14 electrical characteristics .................................................................................................... .......................................15 timing characteristics ........................................................................................................ .......................................18 timing waveforms .............................................................................................................. ......................................19 internal register configuration ............................................................................................... ...................................20 outline diagrams .............................................................................................................. .........................................25 64-pin tqfp ................................................................................................................... ...................................25 ordering information .......................................................................................................... .......................................25 list of figures figures page figure 1. block diagram ....................................................................................................... .......................................5 figure 2. pin assignments ..................................................................................................... .....................................6 figure 3. typical external component conn ections .............................................................................. ...................11 figure 4. typical port termination network .................................................................................... ..........................12 figure 5. crystal circuitry ................................................................................................... .......................................13 figure 6. dn, ctln, and lreq input setup and hold times waveforms ............................................................. ...19 figure 7. dn, ctln output delay relative to sysclk waveforms .................................................................. .......19 list of tables tables page tables 1. signal descriptions ................................................................................................. .....................................7 tables 2. absolute maximum ratings ............................................................................................ ...........................14 tables 3. analog characteristics .............................................................................................. .................................15 tables 4. driver characteristics .............................................................................................. ..................................16 tables 5. device characteristics .............................................................................................. .................................17 tables 6. switching characteristics ........................................................................................... ...............................18 tables 7. clock characteristics .............................................................................................. ..................................18 tables 8. phy register map for the cable environment ......................................................................... ................20 tables 9. phy register fields for the cabl e environment ....................................................................... ................20 tables 10. phy register page 0: port status page ............................................................................. ...................22 tables 11. phy register port status page fields .............................................................................. .....................23 tables 12. phy register page 1: vendor identi fication page .................................................................. ..............24 tables 13. phy register vendor identification page fields .................................................................... .............24
data sheet, rev. 3 fw802b low-power phy ieee 1394 a-2000 may 2004 two-cable transceiver/arbiter device agere systems inc. 3 description (continued) the phy requires either an external 24.576 mhz crystal or crystal oscillator. the internal oscillator drives an internal phase-locked loop (pll), which generates the required 393.216 mhz reference signal. the 393.216 mhz reference signal is internally divided to provide the 49.152 mhz, 98.304 mhz, and 196.608 mhz clock signals that control transmission of the outbound encoded strobe and data information. the 49.152 mhz clock signal is also supplied to the associated llc for synchronization of the two chips and is used for resynchronization of the received data. the powerdown function, when enabled by the pd signal high, stops operation of the pll and disables all circuitry except the cable-not-active (cna) signal circuitry. the phy supports an isolation barrier between itself and its llc. when /iso is tied high, the link interface outputs behave normally. when /iso is tied low, internal differentiating logic is enabled, and the outputs become short pulses, which can be coupled through a capacitor or transformer as described in the ieee 1394 -1995 annex j. to operate with bus-keeper isolation, the /iso pin of the fw802b must be tied high. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in synchronization with the 49.152 mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304 mbits/s, 196.608 mbits/s, or 393.216 mbits/s as the outbound data-strobe information stream. during transmission, the encoded data information is transmitted differentially on the tpa and tpb cable pair(s). during packet reception, the tpa and tpb transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa and tpb cable pair. the received data-strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits are split into two (for s100), four (for s200), or eight (for s400) parallel streams, resynchronized to the local system clock, and sent to the associated llc. the received data is also transmitted (repeated) out of the other active (connected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. the outputs of these comparators are used by the internal logic to determine the arbitration status. the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. this monitor is called bias-detect. the tpbias circuit monitors the value of incoming tpa pair common-mode voltage when local tpbias is inactive. because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. this monitor is called connect-detect. both the tpb bias-detect monitor and tpbias connect-detect monitor are used in suspend/resume signaling and cable connection detection. the phy provides a 1.86 v nominal bias voltage for driver load termination. this bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. the value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 v or 3 v nominal supplies. this bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 f. the transmitter circuitry, the receiver circuitry, and the twisted-pair bias voltage circuity are all disabled with a powerdown condition. the powerdown condition occurs when the pd input is high. the port transmitter circuitry, the receiver circuitry, and the tpbias output are also disabled when the port is disabled, suspended, or disconnected. the line drivers in the phy operate in a high- impedance current mode and are designed to work with external 112 ? line-termination resistor networks. one network is provided at each end of each twisted- pair cable. each network is composed of a pair of series-connected 56 ? resistors. the midpoint of the pair of resistors that is directly connected to the twisted-pair a (tpa) signals is connected to the tpbias voltage signal. the midpoint of the pair of resistors that is directly connected to the twisted-pair b (tpb) signals is coupled to ground through a parallel rc network with recommended resistor and capacitor values of 5 k ? and 220 pf, respectively. the value of the external resistors are specified to meet the standard specifications when connected in parallel with the internal receiver circuits. the driver output current, along with other internal operating currents, is set by an external resistor. this resistor is connected between the r0 and r1 signals and has a value of 2.49 k ? 1%.
fw802b low-power phy ieee 1394 a-2000 data sheet, rev. 3 two-cable transceiver/arbiter device may 2004 4 agere systems inc. description (continued) the fw802b supports suspend /resume as defined in the ieee 1394 a-2000 specification. the suspend mechanism allows an fw802b port to be put into a suspended state. in this state, a port is unable to transmit or receive data packets, however, it remains capable of detecting c onnection status changes and detecting incoming tpbias. when all ports of the fw802b are suspended, all ci rcuits except the bias voltage reference generator and bias detection circuits are powered down, resulting in significant power savings. the use of suspend/resume is recommended. four signals are used as inputs to set four configuration status bits in the self-identification (self- id) packet. these signals are hardwired high or low as a function of the equipment design. pc[0:2] are the three signals that indicate either the need for power from the cable or the ability to supply power to the cable. the fourth signal, c/lkon, as an input, indicates whether a node is a contender for bus manager. when the c/lkon signal is asserted, it means the node is a contender for bus manager. when the signal is not asserted, it means that the node is not a contender. the c bit corresponds to bit 20 in the self- id packet. pc[0:2] corresponds to the pwr field of the self-id packet in the following manner: pc0 corresponds to bit 21, pc1 corresponds to bit 22, and pc2 corresponds to bit 23 (see self-id packets table in section 4.3.4.1 of the ieee 1394 a-2000 standard for additional details). a powerdown signal (pd) is provided to allow a powerdown mode where most of the phy circuits are powered down to conserve energy in battery-powered applications. the internal logic in fw802b is reset as long as the powerdown signal is asserted. a cable status signal, cna, provides a high output when none of the twisted-pair cable ports are receiving incoming bias voltage. this output is not debounced. the cna output can be used to determine when to power the phy down or up. in the powerdown mode, all circuitry is disabled except the cna circuitry. it should be noted that when the device is powe red down, it does not act in a repeater mode. when the power supply of the phy is removed while the twisted-pair cables are connected, the phy transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the tpbias signal voltage on the other end of the cable. whenever the tba/tpb signals are wired to a connector, they must be te rminated using the normal termination network (see figure 4). this is required for reliable operation. for those applications, when one of the fw802b?s ports is not wired to a connector, those unused to a connector, those unused ports may be left unconnected without normal termination. when a port does not have a cable connected, internal connect- detect circuitry will keep the port in a disconnected state. note: all gap counts on all nodes of a 1394 bus must be identical. the software accomplishes this by issuing phy configuration packets (see section 4.3.4.3 of the ieee 1394a-2000 standard) or by issuing two bus resets, which resets the gap counts to the maximum level (3fh). the link power status (lps) signal works with the c/lkon signal to manage the llc power usage of the node. the lps signal indicates that the llc of the node is powered up or powered down. if lps is inac- tive for more than 1.2 s and less than 25 s, the phy/link interface is reset. if lps is inactive for greater than 25 s, the phy will disable the phy/link interface to save power. fw802b continues its repeater function even when the phy/link inte rface is disabled. if the phy then receives a link-on packet, the c/lkon sig- nal is activated to output a 6.114 mhz signal, which can be used by the llc to power itself up. once the llc is powered up, the lps signal communicates this to the phy and the phy/link interface is enabled. the c/lkon signal is turned off when lps is active or when a bus reset occurs, pr ovided the interrupt that caused c/lkon is not present. when the phy/link interface is in the disabled state, the fw802b will automatically enter a low-power mode, if all ports are inactive (disconnected, disabled, or sus- pended). in this low-power mode, the fw802b disables its pll and also disables parts of its reference circuitry depending on the state of the ports (some reference cir- cuitry must remain active in order to detect incoming tp bias). the lowest power consumption (the microlow- power sleep mode) is attained when all ports are either disconnected or disabled with the ports inter- rupt enable bit (see table 11) cleared. the fw802b will exit the low-power mode when the lps input is asserted high or when a port event occurs that requires the fw802b to become active in order to respond to the event or to notify the llc of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). when the fw802b is in the low-power mode, the sysclk output will become ac tive (and the phy/link interface will be initialized and become operative) within 3 ms after lps is asserted high. two of the fw802b?s signals are used to set up various test conditions us ed only during the device manufacturing process. these signals (se and sm) should be connected to v ss for normal operation.
agere systems inc. 5 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 description (continued) 5-5459.f (f) figure 1. block diagram link interface i/o received data decoder/ arbitration and control retimer state machine logic bias voltage and current generator cable port 1 oscillator, pll system, and clock generator transmit data encoder cable port 0 tpa0+ tpa0? tpb0+ tpb0? tpbias0 tpbias1 tpa1+ tpa1? tpb1+ tpb1? xi xo cps lps /iso cna sysclk lreq ctl0 ctl1 d0 d1 d2 d3 c/lkon se sm pd /reset crystal d4 d5 d6 d7 pc0 pc1 pc2 r0 r1
6 6 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 signal information note: active-low signals are indicated by ?/? at the beginning of signal names, within this document. 5-6236.b (f) figure 2. pin assignments lreq v ss ctl0 ctl1 d0 d1 v dd d2 d3 d4 d5 d6 d7 v ss cna lps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc v dda tpbias1 tpa1+ tpa1? tpb1+ tpb1? tpbias0 tpa0+ tpa0? tpb0+ tpb0? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd c/lkon pd pc0 pc1 pc2 /iso cps v ss v dd v dd se sm v dda v dda v ssa 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v ssa v dda v dda v ssa v ssa r0 r1 v ss v dd pll v ss pll xi xo /reset v dd sysclk v ss 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 agere fw802b pin #1 identifier
agere systems inc. 7 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 signal information (continued) table 1. signal descriptions pin signal * type name/description 18 c/lkon i/o bus manager capable input and link-on output. on hardware reset (/reset), this pin is used to set the default value of the contender status indicated during self-id. the bit value programming is done by tying the signal through a 10 k ? resistor to v dd (high, bus manager capable) or to gnd (low, not bus manager capable). using either the pull-up or pull- down resistor allows the link-on output to override the input value when necessary. after hardware reset, this pin is set as an output. if the lps is inactive, c/lkon indicates one of the following events by asserting a 6.114 mhz signal. 1. fw802b receives a link-on packet addressed to this node. 2. port_event register bit is 1. 3. any of the timeout, pwr_fail, or loop register bits are 1 and the watchdog register bit is also 1. 4. once activated, the c/lkon output will continue active until the lps becomes active. the phy also deasserts the c/lkon output when a 1394 bus reset occurs, if the c/lkon is active due solely to the recep- tion of a link-on packet. note: if an interrupt condition exists which would otherwise cause the c/lkon output to be activated if the lps were inactive, the c/lkon output will be activated when the lps subsequently becomes inactive. 15 cna o cable-not-active output. cna is asserted high when none of the phy ports are receiving an incoming bias voltage. this circuit remains active during the powerdown mode. 24 cps i cable power status. cps is normally connected to the cable power through a 400 k ? resistor. this circuit drives an internal comparator that detects the presence of cable power. this information is maintained in one internal register and is available to the llc by way of a register read (see table 8, address register 0000 2 , bit 7/ps). in applications that do not sink or source 1394 power (vp), this pin can be tied to ground. note: when this pin is grounded, the pwr_fail bit in phy register 0101 2 will be set. 3 ctl0 i/o control i/o. the ctln signals are bidirectional communications control signals between the phy and the llc. these signals control the passage of information between the two devices. bus-keeper circuitry is built into these terminals. 4ctl1 5, 6, 8, 9, 10, 11, 12, 13 d[0:7] i/o data i/o. the dn signals are bidirectional and pass data between the phy and the llc. bus-keeper circuitry is built into these terminals. * active-low signals are indicated by ?/? at the beginning of signal names, within this document.
8 8 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 signal information (continued) table 1. signal descriptions (continued) pin signal * type name/description 23 /iso i link interface isolation disable input (active-low). /iso controls the operation of an internal pulse differentiating function used on the phy-llc interface signals, ctln and dn, when they operate as outputs. when /iso is asserted low, the isolation barrier is implemented between phy and its llc (as described in annex j of ieee 1394 -1995). /iso is normally tied high to disable isolation differentiation. bus-keepers are enabled when /iso is high (inactive) on ctln, dn, and lreq. when /iso is low (active), the bus-keepers are disabled. please refer to agere?s application note ieee 1394 isolation (ap98-074cmpr) for more informa- tion. 16 lps i link power status. lps is connected to either the v dd supplying the llc or to a pulsed output that is active when the llc is powered for the purpose of monitoring the llc power status. if lps is inactive for more than 1.2 s and less than 25 s, the phy-link interface is reset. if lps is inactive for greater than 25 s, the phy will disable the phy/link interface to save power. fw802b continues its repeater function. 1lreq i link request. lreq is an output from the llc that requests the phy to perform some service. bus-keeper circuitry is built into this terminal. 44, 45, 46, 47, 48 nc ? no connect. 20 pc0 i power-class indicators. on hardware reset (/reset), these inputs set the default value of the power class indicated during selfid. these bits can be tied to v dd (high) or to ground (low) as required for particular power consumption and source characteristics. in selfid packet (see section 4.3.4.1 of the 1394a-2000 specification ), pc0, the most significant bit of this 3-bit field, corresponds to bit 20, pc1 corresponds to bit 21, and pc2 corresponds to bit 22. as an example, for a power_class value of 001, pc0 = 0, pc1 = 0, and pc2 = 1. 21 pc1 22 pc2 19 pd i powerdown. when asserted high, pd turns off all internal circuitry except the bias-detect circuits that drive the cna signal. internal fw802b logic is kept in the reset state as long as pd is asserted. the pd terminal is provided for backward compatibility. it is recommended that the fw802b be allowed to manage its own power consumption using suspend/resume in conjunction with lps. c/lkon features are defined in the ieee 1394 a- 2000 specification. 57 v dd pll ? power for pll circuit. v dd pll supplies power to the pll circuitry portion of the device. 58 v ss pll ? ground for pll circuit. v ss pll is tied to a low-impedance ground plane. 54 r0 i current setting resistor. an internal reference voltage is applied to a resistor connected between r0 and r1 to set the operating current and the cable driver output current. a low temperature-coefficient resistor (tcr) with a value of 2.49 k ? 1% should be used to meet the ieee 1394 -1995 standard requirements for output voltage limits. 55 r1 * active-low signals are indicated by ?/? at the beginning of signal names, within this document.
agere systems inc. 9 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 61 /reset i reset (active-low). when /reset is asserted low (active), a 1394 bus reset condition is set on the active cable ports and the fw802b is reset to the reset start state. to guarantee that the phy will reset, this pin must be held low for at least 2 ms. an internal pull-up resistor connected to v dd is provided so that only an external delay capacitor (0.1 f) and resistor (510 k ?) , in parallel, are required to connect this pin to ground. this circuitry will ensure that the capacitor will be discharged when phy power is removed. this input is a standard logic buffer and can also be driven by an open-drain logic output buffer. do not leave this pin unconnected. 28 se i test mode control. se is used during agere?s manufacturing test and should be tied to v ss for normal operation. 29 sm i test mode control. sm is used during agere?s manufacturing test and should be tied to v ss for normal operation. 63 sysclk o system clock. sysclk provides a 49.152 mhz clock signal, which is synchronized with the data transfers to the llc. 36 tpa0+ analog i/o port0, port cable pair a. tpa0 is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802b?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a discon- nected state. 35 tpa0 ? 41 tpa1 + analog i/o port1, port cable pair a. tpa1 is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802b?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. 40 tpa1 ? 34 tpb0+ analog i/o port0, port cable pair b. tpb0 is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802b?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. 33 tpb0 ? 39 tpb1 + analog i/o port1, port cable pair b. tpb1 is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differen- tial signal pins should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802b?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. 38 tpb1 ? signal information (continued) table 1. signal descriptions (continued) pin signal * type name/description * active-low signals are indicated by ?/? at the beginning of signal names, within this document.
10 10 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 37 tpbias0 analog i/o portn, twisted-pair bias. (where n refers to the port number). tpbias provides the 1.86 v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. when the fw802b?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-detect circuitry will keep the port in a discon- nected state. 42 tpbias1 7, 17, 26, 27, 62 v dd ? digital power. v dd supplies power to the digital portion of the device. 30, 31, 43, 50, 51 v dda ? analog circuit power. v dda supplies power to the analog portion of the device. 2, 14, 25, 56, 64 v ss ? digital ground. all v ss signals should be tied to the low-impedance ground plane. 32, 49, 52, 53 v ssa ? analog circuit ground. all v ssa signals should be tied together to a low- impedance ground plane. 59 xi ? crystal oscillator. xi and xo connect to a 24.576 mhz parallel resonant fundamental mode crystal. although, when a 24.576 mhz clock source is used, it can be connected to xi with xo left unconnected. the optimum values for the external load capacitors and resistor are dependent on the specifications of the crystal used. it is necessary to add an external series resistor (r l ) to the xo pin (see figures 3 and 5). for more details, refer to the crystal selection considerations section in the data sheet. note that it is very important to place the crystal as close as possible to the xo and xi pins, i.e., within 0.5 in./1.27 cm. 60 xo signal information (continued) table 1. signal descriptions (continued) pin signal * type name/description * active-low signals are indicated by ?/? at the beginning of signal names, within this document.
data sheet, rev. 3 fw802b low-power phy ieee 1394 a-2000 may 2004 two-cable transceiver/arbiter device agere systems inc. 11 application information 5-6767 (f) * see figure 4 for typical port termination network. figure 3. typical external component connections v dd lreq v ss ctl0 ctl1 d0 d1 v dd d2 d3 d4 d5 d6 d7 v ss cna lps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc v dda tpbias1 tpa1+ tpa1? tpb1+ tpb1? tpbias0 tpa0+ tpa0? tpb0+ tpb0? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd c/lkon pd pc0 pc1 pc2 /iso cps v ss v dd v dd se sm v dda v dda v ssa 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v ssa v dda v dda v ssa v ssa r0 r1 v ss v dd pll v ss pll xi xo /reset sysclk v ss 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 agere fw802b llc llc pulse or v dd port 0* llc c l c l 2.49 k ? 24.576 mhz power class 400 k ? cable power port 1* pin #1 identifier 0.1 f 510 k ? r l
12 12 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 application information (continued) 5-6930 (f) figure 4. typical port termination network crystal selection considerations the fw802b is designed to use an external 24.576 mhz parallel resonant fundamental mode crystal connected between the xi and xo terminals to provide the reference for an internal oscillator circuit. the ieee 1394 a-2000 standard requires that fw802b have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. to achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. the total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. tpbias1 tpa1+ tpa1? tpb1+ tpb1? tpbias0 tpa0+ tpa0? tpb0+ tpb0? 42 41 40 39 38 37 36 35 34 33 tpbias1 56 ? 56 ? 56 ? 56 ? 5 k ? 220 pf 0.33 f ieee 1394 -1995 standard connector use same port termination network as illustrated below. 1 3 5 2 4 6 vg vp cable power
agere systems inc. 13 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 crystal selection considerations (continued) load capacitance the frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also capacitances from the fw802b board traces and capacitances of the other fw802b connected components. the values for load capacitors (c a and c b ) should be calculated using this formula: c a = c b = (c l ? c stray ) 2 where: c l = load capacitance specified by the crystal manufacturer cstray = capacitance of the board and the fw802b, typically 2 pf?3 pf r l = load resistance; the value of r l is dependent on the specific crystal used. please re fer to your crystal manufacturer?s data sheet and application notes to determine an appropriate value. figure 5. crystal circuitry adjustment to crystal loading the resistor (r l) in figure 5 is recommended for fine-tuning the crystal circuit. the value for this resistor is depen- dent on the specific crystal used. please refer to your crystal manufacturer?s data sheet and application notes to determine an appropriate value for r l . a more precise value for this resistor can be obtained by placing different values of r l on a production board and using an oscilloscope to view the resultant clock waveform at node a for each resistor value. the desired waveform should have the following characteristics: the waveform should be sinu- soidal, with an amplitude as large as possible, but not greater than 3.3 v or less than 0 volts. crystal/board layout the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency and minimizing noise introduced into the fw802b pll. the crystal and two load capacitors (c a + c b ) should be considered as a unit during layout. they should be placed as close as possible to one another, while minimizing the loop area cre- ated by the combination of the three components. minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. this layout unit (crystal and load capacitors) should then be placed as close as possible to the phy xi and xo terminals to minimize trace lengths. vias should not be used to route the xi and xo signals. 1394 application support contact information e-mail: support1394@agere.com c b c a xi xo r l a
14 14 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 2. absolute maximum ratings * except for 5 v tolerant i/o (ctl0, ctl1, d0?d7, and lreq) where v i max = 5.5 v. parameter symbol min max unit supply voltage range v dd 3.0 3.6 v input voltage range* v i ? 0.5 v dd + 0.5 v output voltage range at any output v o ? 0.5 v dd + 0.5 v operating free air temperature t a 070 c storage temperature range t stg ?65 150 c
agere systems inc. 15 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 electrical characteristics table 3. analog characteristics parameter test conditions symbol min typ max unit supply voltage source power node v dd?sp 3.0 3.3 3.6 v differential input voltage cable inputs, 100 mbits/s operation v id?100 142 ? 260 mv cable inputs, 200 mbits/s operation v id?200 132 ? 260 mv cable inputs, 400 mbits/s operation v id?400 100 ? 260 mv cable inputs, during arbitration v id?arb 168 ? 265 mv common-mode voltage source power mode tpb cable inputs, speed signaling off v cm 1.165 ? 2.515 v tpb cable inputs, s100 speed signaling on v cm?sp?100 1.165 ? 2.515 v tpb cable inputs, s200 speed signaling on v cm?sp?200 0.935 ? 2.515 v tpb cable inputs, s400 speed signaling on v cm?sp?400 0.532 ? 2.515 v common-mode voltage nonsource power mode* * for a node that does not source power (see section 4.2.2.2 in ieee 1394 -1995 standard). tpb cable inputs, speed signaling off v cm 1.165 ? 2.015 v tpb cable inputs, s100 speed signaling on v cm?nsp?100 1.165 ? 2.015 v tpb cable inputs, s200 speed signaling on v cm?nsp?200 0.935 ? 2.015 v tpb cable inputs, s400 speed signaling on v cm?nsp?400 0.532 ? 2.015 v receive input jitter tpa, tpb cable inputs, 100 mbits/s operation ???1.08ns tpa, tpb cable inputs, 200 mbits/s operation ???0.5ns tpa, tpb cable inputs, 400 mbits/s operation ???0.315ns receive input skew between tpa and tpb cable inputs, 100 mbits/s operation ???0.8ns between tpa and tpb cable inputs, 200 mbits/s operation ???0.55ns between tpa and tpb cable inputs, 400 mbits/s operation ???0.5ns positive arbitration comparator input threshold voltage ?v th +89?168mv negative arbitration comparator input threshold voltage ?v th ? ?168 ? ?89 mv speed signal input threshold voltage 200 mbits/s v th?s200 45 ? 139 mv 400 mbits/s v th?s400 266 ? 445 mv output current tpbias outputs i o ?5 ? 2.5 ma tpbias output voltage at rated i/o current v o 1.665 ? 2.015 v current source for connect detect circuit ?i cd ??76 a
16 16 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 electrical characteristics (continued) table 4. driver characteristics parameter test conditions symbol min typ max unit differential output voltage 56 ? load v od 172 ? 265 mv off-state common-mode voltage drivers disabled v off ??20mv driver differential current, tpa+, tpa ? , tpb+, tpb ? driver enabled, speed signaling off* * limits are defined as the algebraic sum of tpa+ and tpa ? driver currents. limits also apply to tpb+ and tpb ? as the algebraic sum of driver currents. ? limits are defined as the absolute limit of each of tpb+ and tpb ? driver currents. i diff ? 1.05 ? 1.05 ma common-mode speed signaling current, tpb+, tpb ? 200 mbits/s speed signaling enabled ? i sp ? 2.53 ? ? 4.84 ma 400 mbits/s speed signaling enabled ? i sp ? 8.1 ? ? 12.4 ma
agere systems inc. 17 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 electrical characteristics (continued) table 5. device characteristics * device is capable of both differentiated and undifferentiated operation. parameter test conditions symbol min typ max unit supply current: one port active all ports active no ports active, (microlow- power sleep mode) lps = 0 pd = 1 v dd = 3.3 v i dd i dd i dd i dd ? ? ? ? 54 74 50 50 ? ? ? ? ma ma a a high-level output voltage i oh max, v dd = min v oh v dd ? 0.4 ? ? v low-level output voltage i ol min, v dd = max v ol ??0.4v high-level input voltage cmos inputs v ih 0.7 v dd ?? v low-level input voltage cmos inputs v il ? ? 0.2 v dd v pull-up current, /reset input v i = 0 v i i 11 ? 32 a powerup reset time, /reset input v i = 0 v ? 2 ? ? ms rising input threshold voltage /reset input ?vi rst 1.1 ? 1.4 v output current sysclk i ol /i oh @ ttl ?16 ? 16 ma control, data i ol /i oh @ cmos ?12 ? 12 ma cna i ol /i oh ?16 ? 16 ma c/lkon i ol /i oh ?2 ? 2 ma input current, lreq, lps, pd, se, sm, pc[0:2] inputs v i = v dd or 0 v i i ?? 1 a off-state output current, ctl[0:1], d[0:7], c/lkon i/os v o = v dd or 0 v i oz ?? 5 a power status input threshold voltage, cps input 400 k ? resistor v th 7.5 ? 8.5 v rising input threshold voltage*, lreq, ctln, dn ?v it +v dd /2 + 0.3 ? v dd /2 + 0.8 v falling input threshold voltage*, lreq, ctln, dn ?v it ? v dd /2 ? 0.8 ? v dd /2 ? 0.3 v bus holding current, lreq, ctln, dn v i = 1/2(v dd ) ? 250 ? 550 a rising input threshold voltage lps ?v lih ? ? 0.24 v dd + 1 v falling input threshold voltage lps ?v lil 0.24 v dd + 0.2 ? ? v
18 18 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 timing characteristics table 6. switching characteristics table 7. clock characteristics symbol parameter measured test conditions min typ max unit ? jitter, transmit tpa, tpb ? ? ? 0.15 ns ? transmit skew between tpa and tpb ??? 0.1 ns t r rise time, transmit (tpa/tpb) 10% to 90% r i = 56 ?, c i = 10 pf ??1.2ns t f fall time, transmit (tpa/tpb) 90% to 10% r i = 56 ?, c i = 10 pf ??1.2ns t su setup time, dn, ctln, lreq to sysclk 50% to 50% see figure 6. 6 ? ? ns t h hold time, dn, ctln, lreq from sysclk 50% to 50% see figure 6. 0 ? ? ns t d delay time, sysclk to dn, ctln 50% to 50% see figure 7. 1 ? 6 ns parameter symbol min typ max unit external clock source frequency f 24.5735 24.5760 24.5785 mhz
agere systems inc. 19 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 timing waveforms 5-6017.a (f) figure 6. dn, ctln, and lreq input setup and hold times waveforms 5-6018.a (f) figure 7. dn, ctln output delay relative to sysclk waveforms sysclk dn, ctln, lreq tsu th sysclk dn, ctln td
20 20 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 internal register configuration the phy register map is shown below in table 8. (refer to ieee 1394 a-2000, 5b.1 for more information). table 8. phy register map for the cable environment the meaning of the register fields within the phy register map are defined by table 9 below. power reset values not specified are resolved by the operation of the phy state machines subsequent to a power reset. table 9. phy register fields for the cable environment address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0000 2 physical_id r ps 0001 2 rhb ibr gap_count 0010 2 extended (7) xxxxx to ta l_ p o r ts 0011 2 max_speed xxxxx delay 0100 2 lctrl contender jitter pwr_class 0101 2 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 0111 2 page_select xxxxx port_select 1000 2 register 0 page_select 1111 2 register 7 page_select required xxxxx reserved field size type power reset value description physical_id 6 r 000000 the address of this node determined during self-identification. a value of 63 indicates a malconfigured bus; the link will not transmit any packets. r 1 r 0 when set to one, indicates that this node is the root. ps 1 r ? cable power active. rhb 1 rw 0 root hold-off bit. when set to one, the force_root variable is true, which instructs the phy to attempt to become the root dur- ing the next tree identify process. ibr 1 rw 0 initiate bus reset. when set to one, instructs the phy to set ibr true and reset_time to reset_time. these values in turn cause the phy to initiate a bus reset without arbitration; the reset signal is asserted for 166 s. this bit is self-clearing. gap_count 6 rw 3f 16 used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. see section 4.3.6 of ieee standard 1394a -2000 for the encoding of this field. extended 3 r 7 this field has a constant value of seven, which indicates the extended phy register map.
agere systems inc. 21 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 internal register configuration (continued) table 9. phy register fields for the cable environment (continued) field size type power reset value description total_ports 4 r 2 the number of ports implemented by this phy. this count reflects the number. max_speed 3 r 010 2 indicates the speed(s) this phy supports: 000 2 = 98.304 mbits/s 001 2 = 98.304 and 196.608 mbits/s 010 2 = 98.304, 196.608, and 393.216 mbits/s 011 2 = 98.304, 196.608, 393.216, and 786.43 mbits/s 100 2 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 mbits/s 101 2 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 mbits/s all other values are reserved for future definition. delay 4 r 0000 worst-case repeater delay, expressed as 144 + (delay * 20) ns. lctrl 1 rw 1 link active. cleared or set by software to control the value of the l bit transmitted in the node?s self-id packet 0, which will be the logical and of this bit and lps active. contender 1 rw see description. cleared or set by software to control the value of the c bit transmitted in the self-id packet. powerup reset value is set by c/lkon pin. jitter 3 r 000 the difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. pwr_class 3 rw see description. power-class. controls the value of the pwr field transmitted in the self-id packet. see section 4.3.4.1 of ieee standard 1394 a-2000 for the encoding of this field. pc0, pc1, and pc2 pins set up power reset value. watchdog 1 rw 0 when set to one, the phy will set port_event to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bus reset. a write of one to this bit instructs the phy to set isbr true and reset_time to short_reset_time. these values in turn cause the phy to arbitrate and issue a short bus reset. this bit is self-clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 1 cable power failure detect. set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero. timeout 1 rw 0 arbitration state machine timeout. a write of one to this bit clears it to zero (see max_arb_state_time). port_event 1 rw 0 port event detect. the phy sets this bit to one if any of con- nected, bias, disabled, or fault change for a port whose int_enable bit is one. the phy also sets this bit to one if resume operations commence for any port and watchdog is one. a write of one to this bit clears it to zero.
22 22 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 internal register configuration (continued) table 9. phy register fields for the cable environment (continued) the port status page is used to access configuration and status information for each of the phy?s ports. the port is selected by writing zero to page_select and the desired port number to port_select in the phy register at address 0111 2 . the format of the port status page is illustrated by table 10 below; reserved fields are shown shaded. the meanings of the register fields with the port status page are defined by table 11. table 10. phy register page 0: port status page field size type power reset value description enab_accel 1 rw 0 enable arbitration acceleration. when set to one, the phy will use the enhancements specified in section 4.4 of 1394 a-2000 specification. phy behavior is unspecified if the value of enab_accel is changed while a bus request is pending. enab_multi 1 rw 0 enable multispeed packet concatenation. when set to one, the link will signal the speed of all packets to the phy. page_select 3 rw 000 selects which of eight possible phy register pages are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. port_select 4 rw 000 if the page selected by page_select presents per-port information, this field selects which port?s registers are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. ports are numbered monotonically starting at zero, p0. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 astat bstat child connected bias disabled 1001 2 negotiated_speed int_enable fault xxxxx xxxxx xxxxx 1010 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1011 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1100 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1101 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1111 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx required xxxxx reserved
agere systems inc. 23 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 internal register configuration (continued) the meaning of the register fields with the port status page are defined by table 11 below. table 11. phy register port status page fields field size type power reset value description astat 2 r ? tpa line state for the port: 00 2 = invalid 01 2 = 1 10 2 = 0 11 2 = z bstat 2 r ? tpb line state for the port (same encoding as astat). child 1 r 0 if equal to one, the port is a child; otherwise, a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy transitions to state t1: child hand- shake during the tree identify process (see section 4.4.2.2 in ieee standard 1394 -1995). connected 1 r 0 if equal to one, the port is connected. bias 1 r 0 if equal to one, incoming tpbias is detected. disabled 1 rw 0 if equal to one, the port is disabled. negotiated_speed 3 r 000 indicates the maximum speed negotiated between this phy port and its immediately connected port; the encoding is the same as for the phy register max_speed field. int_enable 1 rw 0 enable port event interrupts. when set to one, the phy will set port_event to one if any of connected, bias, disabled, or fault (for this port) change state. fault 1 rw 0 set to one if an error is detected during a suspend or resume operation. a write of one to this bit clears it to zero.
24 agere systems inc. data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 internal register configuration (continued) the vendor identification page is used to identify the phy?s vendor and compliance level. the page is selected by writing one to page_select in the phy register at address 0111 2 . the format of the vendor identification page is shown in table 12; reserved fields are shown shaded. table 12. phy register page 1: vendor identification page the meaning of the register fields within the vendor identification page are defined by table 13. table 13. phy register vendor identification page fields the vendor-dependent page provides access to information used in manufacturing test of the fw802b. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 compliance_level 1001 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1010 2 1011 2 vendor_id 1100 2 1101 2 1110 2 product_id 1111 2 required xxxxx reserved field size type description compliance_level 8 r standard to which the phy implementation complies: 0 = not specified 1 = ieee 1394 a-2000 agere?s fw802b compliance level is 1. all other values reserved for future standardization. vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy. agere?s vendor id is 00601d 16 . this number is obtained from the ieee registration authority committee (rac). the most significant byte of vendor_id appears at phy register location 1010 2 and the least significant at 1100 2 . product_id 24 r the meaning of this number is determined by the company or organization that has been granted vendor_id. agere?s fw802b product id is 080201 16 . the most significant byte of product_id appears at phy register location 1101 2 and the least significant at 1111 2 .
agere systems inc. 25 data sheet, rev. 3 may 2004 two-cable transceiver/arbiter device fw802b low-power phy ieee 1394 a-2000 outline diagrams 64-pin tqfp d imensions are in millimeters . 5-3080 (f ) o rdering information * in an effort to better serve its customers and the environment, agere is switching to lead-free packaging on this product (no intentional addition of lead). device code package comcode fw802b-db 64-pin tqfp 700032322 L-FW802B-DB 64-pin tqfp (lead-free)* 700067297 detail a 0.50 typ 1.60 max seating plane 0.08 detail b 0.05/0.15 1.40 0.05 10.00 0.20 12.00 0.20 1 64 49 16 17 32 48 33 10.00 0.20 12.00 0.20 pin #1 identifier zone detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 detail b 0.19/0.27 0.08 m 0.106/0.200
agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere is a registered trademark of agere systems, inc. agere systems and the agere logo are trademarks of agere systems inc. copyright ? 2004 agere systems inc. all rights reserved may 2004 ds02-355cmpr-3 (replaces ds02-355cmpr-2) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44)1344 296 400 1394 is a trademark and ieee is a registered trademark of the institute of electrical and electronics engineers, inc. the firewire logo is a trademark and firewire is a registered trademark of apple computer, inc.

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